1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a data receiving apparatus and control method thereof, and more particularly, to a data receiving apparatus and control method thereof communicating through an I2C (Inter-Integrated Circuit) bus.
2. Description of the Related Art
Generally, a data receiving apparatus, of the type which receives data such as a video signal, an audio signal, etc., communicates through an I2C (bus, a UART (universal asynchronous receiver transmitter) bus, or the like to exchange data.
I2C communication, which utilizes an I2C bus to communicate between devices, includes a clock signal and a data signal line. For example, I2C communication may be used to send and receive information between a CPU, a memory, and an I/O device. Further, I2C communication uses a two-line serial bus, where one line is for sending/receiving the clock signal and the other is for the data signal.
As a consequence of using only two lines, I2C communication provides for a simplified configuration of the data receiving apparatus. In addition, the communication method between devices may also be simplified. As a result I2C communication is widely used.
For example, an I2C communication method where communication between devices occurs through signal transmission using the clock signal line and the data signal line may be set up as shown in Table 1.
TABLE 18 bit1 bit8 bit1 bit8 bit1 bitstartslaveACKsub-ACKdataACKstopad-addressdresstypeacknowl-kind ofacknowl-acknowl-of ICedgefunctionedgeedge
Each line of the I2C bus may be connected to a plurality of devices. When a user controls the plurality of devices, the data receiving apparatus may read and store the data into the devices as in the following process. A controller which controls the devices outputs a start signal to the I2C bus. Further, the controller outputs a slave address to the I2C bus. The slave address may be predetermined for each device, so that each device to be controlled by the controller is identified by a corresponding slave address. The device which is identified by the slave address may be on standby when the slave address is received. The device outputs an acknowledge (ACK) signal to the I2C bus. The ACK signal informs that the device identified by the slave address has normally received the signal from the controller. The sub-addresses correspond to functions which are predetermined in the devices. In addition, the devices may communicate with other devices through the I2C bus. The controller outputs the sub-address to a device which is on standby. When the device receives the sub-address, the device outputs the ACK signal and the data signal through the I2C bus. The device outputs the ACK signal again after the data signal. Then, the controller outputs a stop signal to inform the device of the end of the I2C communication.
During I2C communication the start signal, the stop signal, etc. are classified according to the following method.
TABLE 2startstopACKdataClock signalHighHigh↑↑Data signal↓↑LowLow: 0,High: 1
For example, five volts (5V) indicates the high state of the clock signal and the data signal, respectively. Further, zero volts (0V) indicates that the clock signal and the data signal are respectively in a low state. When the state of the clock signal is high, if the data signal in the high state transitions to the low state data signal, the devices communicating through the I2C bus recognize the signals as the start signal.
When the state of the clock signal is high, if the data signal in the low state transitions to the high state data signal, the devices communicating through the I2C bus recognize the signals as the stop signal. When the state of the data signal is low, if the clock signal in the low state transitions to the high state clock signal, the devices recognize the data as 0. When the state of the data signal is high, if the clock signal in the low state transitions to the high state clock signal, the devices recognize the data as 1.
However, when both the clock signal and the data signal are lower than 5V and higher than 0V, the clock signal and the data signal are not in the high and low state. In this case, the clock signal and the data signal may respectively be represented in the manner of table 2 such as ↑ ↑, ↑ ↓, ↓ ↑, ↓ ↓.
However, ↑ ↑, ↑ ↓, ↓ ↑, ↓↓ do not correspond to a state described in table 2, so that the devices communicating through the I2C bus recognize the clock/data signals as an error.
In other words, the device communicating through the I2C bus sends and/or receives a plurality of signals through each line. When the input states of the clock signal and data signal are converted almost at the same time, each of the clock signal and the data signal may not to be in the high state and the low state so that an error may occur. Further, in the case where a data receiving apparatus which includes an HDCP (high-bandwidth digital content protection) function receives signals through the I2C bus which are not in a high state or low state, and the signals may not be processed properly.